Modern integrated circuits are constructed with up to several million active devices, such as transistors and capacitors, formed in and on a semiconductor substrate. Interconnections between the active devices are created by providing a plurality of conductive interconnection layers, such as polycrystalline silicon and metal, which are etched to form conductors for carrying signals. The conductive layers and interlayer dielectrics are deposited on the silicon substrate wafer in succession, with each layer being, for example, on the order of 1 micron in thickness.
A gate structure is an element of a transistor. FIG. 1 illustrates an example of a gate stack 8. A semiconductor substrate 10 supports a gate insulating layer 16, which overlaps doped regions (source/drain regions) in the substrate (12 and 14), and the gate insulating layer supports a gate 18, which is typically polycrystalline silicon. On the gate is a metallic layer 30. The metallic layer may be separated from the gate by one or more other layers, such as nitrides, oxides, or silicides, illustrated collectively as barrier layer 20. The metallic layer may in turn support one or more other layers (collectively 40), such as nitrides, oxides, or silicides. Oxide 22 may be formed on the sides of the gate to protect the gate oxide at the foot of the gate stack; and insulating spacers 24 may be formed on either side of the gate stack. Furthermore, contacts to the source/drain regions in the substrate, and to the gate structure, may be formed.
Self-aligned contacts (SAC) allow the design of a semiconductor device to have a distance between the gate and the via contact to the substrate, to be at most one-half the minimum gate width. Typically, SAC uses a nitride layer on the gate stack, together with spacers that include nitride, to prevent a misaligned contact from contacting the gate itself. If the nitride were not present, then the etch used to form the hole which will become the contact would pass through the dielectric layer all the way to the gate. When present, the nitride layer and spacers acts as an etch stop, preventing misalignment from forming a hole all the way to the gate, and therefore allowing design of the device to have a much smaller average distance between the contact and the gate.
The nitride layer on the gate stack has at least a thickness of 800 angstroms when used for forming SAC. If used only for other purposes, such as an etch-stop layer or a hard mask, a thickness of less than 800 angstroms is used. Also, the thickness of at least 800 angstroms is the thickness after the dielectric layer has been formed; the nitride layer is usually thicker when originally formed, allowing for a loss of about 500 angstroms during the gate etch (i.e. thickness for the hard mask function), and a loss of about 200 angstroms during nitride spacer formation.
There is an ongoing need to reduce the size of the elements within integrated circuits and semiconductor structures. As the size of an element is reduced, shorter wavelength radiation is need to for exposing the photoresist in order to obtain the smaller features desired. Consequently, photoresists sensitive to the shorter wavelength radiation must also be used. In order to obtain features on the order of 0.1 micron, radiation having a wavelength of 193 nm is used, and the photoresists sensitive to this wavelength are referred to as 193 nm resists. A variety of these resists are commercially available, such as T9269 (from Clariant International, Ltd., Muttenz, Switzerland), 6A100 (Tokyo Ohka Kogyo, Kawasaki-shi, Japan), and AR414 and AR237 (both from Japan Synthetic Rubber Co., Ltd., Tokyo, Japan).
An undesirable problem that arises, however, is that the etching processes have been optimized for the specific photoresists, and switching to different photoresists along with a reduction is scale, can result in problems, such as an increase in line-edge roughness (see “An Experimentally Validated Analytical Model For Gate Line-Edge Roughness (LER) Effects on Technology Scaling” Diaz, C. H., et al., IEEE Electronic Device Letters, Vol. 22, No. 6, pp. 287–89 (June 2001)). Increased line-edge roughness will result in device deficiencies, and a reduction in device yield.